The present invention relates generally to the use of a serial bus in a modular computer. More particularly, the invention is directed to the use of a controller to extend the address range of a serial bus used to access memory devices in multiple modules of a computer system.
Recent trends in computer system designs suggest a strong preference for the use of parallel architectures and multichip configurations of computer processors and memory. Parallel processor computer architectures inherently introduced the concept of modular designs, namely designs which lend themselves to upgrades through the addition of modularized units. The concept of a modular and expandable computer system introduces the need for a system architecture which can recognize and manage changes to the number and type of the modules. In the context of such a multiprocessor system, the diversity of the modules can broadly encompass field replaceable processor, memory, I/O, power supply, or most any other computer units which can be modularized and easily interconnected.
The movement toward multiprocessor modular designs and field replaceability requires that the modules contain vital product information, such as data specifying the module type (e.g., processor versus memory), size and performance characteristics. Furthermore, experience has shown that the memory used to store vital product data can also be used to store other module related information, such as that representing an address relationship between the installed module and the multiprocessor system. Therefore, it is desirable to use electrically erasable programmable read-only memories (EEPROMs) in the modules subject to field replacement to store such vital product data and multiprocessor modular relationship unique data.
It is fairly well known that pin count limitations are major constraints for multichip modules. For this reason, the reading and writing of vital product and configuration data from the modules is preferably accomplished using a serial bus, requiring only a clock line and a data line.
As the number of modules in multiprocessor systems increase, so to do the number of memories units individually associated with the modules. A fully configured multiprocessor system may require as many as 75 modules, inherently requiring the selective and distinct addressing of 75 different memories.
One industry standard serial bus architecture which has evolved over many years to be well documented, frequently used and extensively supported by integrated circuit devices is the I.sup.2 C bus. The particulars of the bus protocol are set forth in the document entitled "The I.sup.2 C-Bus and How To Use It" (including specification) as appears in a Jan. 1992 publication by Signetics Division of Philips. The use of such an industry standard bus is clearly preferred over a completely new and proprietary serial bus for new multiprocessor systems.
The unfortunate deficiency of the I.sup.2 C bus protocol lies in the fact that the chip select is accomplished in a seven bit word which by protocol definition assigns four of the seven bits to a designation of the device type. This protocol leaves the remaining three bits to select among the devices of that device type. For example, the protocol requires that the first four bits of an EEPROM type device select address have a specified binary combination, leaving the last three bits to make the chip selection. The problem with this protocol is that it does not allow differentiation among more than eight EEPROM devices on the I.sup.2 C bus.
The I.sup.2 C bus protocol does provide for the transmission and receipt of ten bit words. However, the ten bit word protocol requires intelligent processing at both the transmission and receiving ends of the communication path over the bus.
The dilemma is how to use a low cost and industry standard bus to select memory having vital product data in modules whose number count is greater than the selection range allowed by the bus protocol.
According to the present invention the bus address range limitation is solved in a modular computer using a memory access system comprising one or more first modules, the first modules having a first memory and an access control means interfaced to a bus, a plurality of second modules, the second modules having a second memory without access control means interfaced to the bus, and means for having the access control means regulate access from the bus both to first memory and to second memory responsive to intelligent signals on the bus. In another form, the invention is directed to a method for accomplishing the functions.
A preferred implementation of the present invention in a modular multiprocessor involves the use of an I.sup.2 C bus to interconnect EEPROM devices which are individually enabled by power application or chip select using shared microcontrollers responsive to intelligent commands transmitted over the same serial bus. In the preferred implementation, each field replaceable module incorporates a EEPROM device for storing vital product data representative of that module. However, the enablement of the EEPROM device for purposes of reading or writing stored data is accomplished in response to a microcontroller which controls two or more EEPROM devices.
The microcontroller responds to extended length words on the serial bus to identify itself as the microcontroller managing access to a group of EEPROM devices. The microcontroller so addressed enables the associated EEPROM devices either by initiating a chip select or enabling power. Thereafter, conventional I.sup.2 C protocol addressing selects the EEPROM device using the same serial bus. Accessing of the EEPROM device so identified permits not only conventional reading of vital product information, but programming/writing of information into the EEPROM for an EEPROM in a replacement module undergoing an initialization sequence.
The system and method of the present invention allow the use of an industry standard serial bus with conventional integrated circuit devices and microcontrollers to address devices greater in numerical count than the bus protocol provides. These and other features of the invention will be more clearly understood and appreciated upon considering the detailed description set forth hereinafter.